1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor.
2. Description of the Related Art
The demands for reduction in chip area with respect to memory LSI, system LSI, and other semiconductor devices, are increasing each year, coupled with the miniaturization of information communications equipment in recent years. It is desired, therefore, that memory cell areas be reduced with the conventional electrical characteristics of transistors being maintained. Vertical transistors are employed as an approach to implementing such reduction in cell area. Conventional vertical transistors include: a type in which, as disclosed in Japanese Patent Laid-open No. 2001-320031, a hole is formed in the thin film formed on a silicon substrate and a vertical transistor has its channel embedded in the hole; a type in which, as disclosed in Japanese Patent Laid-open No. 10-107286, a hole is formed in a silicon substrate and a side of the hole is used as a channel; and a type in which, as disclosed in Japanese Patent Laid-open No. 10-326879, a protrusion of silicon is formed on a silicon substrate and used as a channel.
The conventional vertical transistors require preventive measures against the deterioration of their electrical characteristics, increases in the nonuniformity of the characteristics, and other events. In embodiments of the aforementioned conventional technologies, however, concrete preventive measures are not incorporated against decreases in product yield or against performance deterioration. The present inventors have studied the fact that the deterioration of electrical characteristics and increases in the nonuniformity thereof, caused by excessive stresses in comparison with those of conventional lateral transistors, result in product yield decreases and performance deterioration becoming problems. That is to say, the present inventors have studied the fact that the above is associated with several problems. More specifically, since the region for forming a channel is excessively stressed, drain current “ids” is affected by the stress. Also, since the stress on a gate oxide film also becomes excessive similarly, the leakage current in the gate oxide film increases. In addition, nonuniform processing of the silicon section including the channel region easily changes the internal stress thereof and the stress on the gate oxide film, thus increasing not only drain current “ids”, but also the leakage current in the gate oxide film and the nonuniformity of withstand voltage characteristics.